Hi, I am Esteban Tlelo Cuautle, My LiveDNA is 52.844
 
   
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Dr. Esteban Tlelo Cuautle
 
Highest Degree: Ph.D. in Electronics from Instituto Nacional de Astrofisica, Opticay Electronica, Mexico
 
Institute: Instituto Nacional de Astrofisica, Opticay Electronica, Mexico
 
Area of Interest: Physical Science Engineering
  •   Integrated Circuit Design and Optimization
  •   Chaos Generators Design and Applications
  •   Evolutionary Algorithms
  •   Electronic Circuits
 
URL: http://livedna.org/52.844
 
My SELECTED Publications
1:   Diaz, M.A., J.G. Sanchez, M.A. Garcia, C.E. Tlelo, 2003. A four-quadrant analog multiplier biased at 1.2v working in current-mode. WSEAS Trans. Syst., 1: 1-4.
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2:   Garcia-Ortega, J.M., E. Tlelo-Cuautle and C. Sanchez-Lopez, 2007. Design of current-mode Gm-C filters from the transformation of opamp-RC filters. J. Applied Sci., 7: 1321-1326.
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3:   Pena-Perez, A., E. Tlelo-Cuautle, A. Diaz-Mendez and C. Sanchez-Lopez, 2007. Diseno de un CFOA compatible con CMOS y su aplicacion en filtros analogicos, IEEE Latin America Transactions, 5: 72-76.
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4:   Peña-Perez, A., E. Tlelo-Cuautle and A. Díaz-Mendez, 2007. Diseño de un CFOA Compatible en Tecnología CMOS y su Aplicación en Circuitos Lineales y No Lineales. Científica, 11: 121-127.
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5:   Sanchez-Lopez, C., A. Diaz-Sanchez and E. Tlelo-Cuautle, 2002. Generating gaussian functions using low-voltage MOS-translinear circuits. WSEAS Trans Syst., 2: 190-197.
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6:   Tlelo, E., C. Sanchez, F. Sandoval and G. Flores, 2004. Symbolic analysis of analog electronic circuits by manipulation of data structures. Informacion Tecnologica, 15: 101-104.
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7:   Tlelo-Cuautle, E. and A. Sarmiento-Reyes, 2003. A pure nodal analysis method suitable for analog circuits using nullors. J. Applied Res. Technol., 1: 235-247.
8:   Tlelo-Cuautle, E. and C. Sanchez-López, 2004. Symbolic computation of NF of transistor circuits. IEICE Trans. Fundamentals Electron, Commun. Comput. Sci., E87: 2420-2425.
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9:   Tlelo-Cuautle, E. and J. Aguila-Meza, 2005. Enhancing the symbolic analysis of analog circuits. J. Applied Res. Technol., 3: 150-160.
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10:   Tlelo-Cuautle, E. and J.M. Munoz-Pacheco, 2007. Numerical simulation of Chua's circuit oriented to circuit synthesis. Int. J. Nonlinear Sci. Numerical Simulation, 8: 249-256.
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11:   Tlelo-Cuautle, E. and M.A. Duarte-Villaseñor, 2006. Designing Chua's circuit from the behavioral to the transistor level of abstraction. Applied Mathematics and Computation, 184: 715-720.
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12:   Tlelo-Cuautle, E., D. Moro-Frias, C. Sanchez-Lopez, M.A. Duarte-Villasenor, 2008. Synthesis of CCII-s by superimposing VFs and CFs through genetic operations. IEICE Electronics Express, 5: 411-417.
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13:   Tlelo-Cuautle, E., J.M. Munoz-Pacheco and J. Martinez-Carballido, 2007. Frequency scaling simulation of Chua's circuit by automatic determination and control of step-size. Applied Mathematics and Computation, 194: 486-491.
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14:   Tlelo-Cuautle, E., A. Gaona-Hernandez and J. García-Delgado, 2006. Implementation of a chaotic oscillator by designing Chua's diode with CMOS CFOAs. Analog Integrated Circuits and Signal Processing, 48: 159-162.
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15:   Tlelo-Cuautle, E., A. Quintanar-Ramos, G. Gutierrez-Perez and M. Gonzalez de la Rosa, 2004. SIASCA: Interactive system for the symbolic analysis of analog circuits. IEICE Electron. Express, 1: 19-23.
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16:   Tlelo-Cuautle, E., A.R. Quintanar, G.P. Gutierrez, M.R. Gonzalez and S. Fuentes-Goiz, 2004. Interactive system for the symbolic analysis of analog circuits. WSEAS Trans on Circuits and Syst., 3: 810-812.
17:   Tlelo-Cuautle, E., C. Sanchez-López and F. Sandoval-Ibarra, 2005. Computing symbolic expressions in analog circuits using nullors. Computación y Sistemas, 9: 119-132.
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18:   Tlelo-Cuautle, E., C. Sanchez-López, G. Flores-Becerra and F. Sandoval-Ibarra, 2003. Symbolic analysis: improving the formulation approach of analog circuits. WSEAS Trans. Circuits, 1: 297-300.
19:   Tlelo-Cuautle, E., D. Torres-Muñoz and L. Torres-Papaqui, 2005. On the computational synthesis of CMOS voltage followers. IEICE Transactions on Fundamentals of Electronics, Communications and Comput. Sci., E88: 3479-3484.
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20:   Tlelo-Cuautle, E., M.A. Duarte-Villasenor and I. Guerra-Gomez, 2008. Automatic synthesis of VFs and VMs by applying genetic algorithms. Circuits Syst. Signal Process., 27: 391-403.
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21:   Tlelo-Cuautle, E., M.A. Duarte-Villasenor and J.M. Garcia-Ortega, 2007. Modelado y Simulacion de un oscilador caotico usando MATLAB. IEEE Latin America Transactions, 5: 95-98.
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22:   Tlelo-Cuautle, E., M.A. Duarte-Villasenor, C.A. Reyes-Garcia and G. Reyes-Salgado, 2007. Automatic synthesis of electronic circuits using genetic algorithms. Computación y Sistemas, 10: 217-229.
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23:   Tlelo-Cuautle, E., M.A. Duarte-Villasenor, J.M. Garcia-Ortega and C. Sanchez-Lopez, 2007. Designing SRCOs by combining SPICE and Verilog-A. Int. J. Electronics, 94: 373-379.
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24:   Torres-Munozy, D. and E. Tlelo-Cuautle, 2004. Synthesis of voltage mode and current mode filters by using a universal active device. Informacion Tecnologica, 15: 59-62.
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25:   Torres-Muñoz, D., E. Tlelo-Cuautle, A. Díaz-Mendez and A. Díaz-Sanchez, 2003. Adjoint transformations in OTA-C filters using nullors. WSEAS Trans. Syst., 2: 354-357.
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26:   Torres-Papaqui, L. and E. Tlelo-Cuautle, 2004. Analog circuit synthesis: A proposed approach to design VFs. WSEAS Trans. on Circuits and Syst., 3: 813-815.
27:   Torres-Papaqui, L., D. Torres-Munoz and E. Tlelo-Cuautle, 2006. Synthesis of VFs and CFs by manipulation of generic cells. Analog Integrated Circuits and Signal Processing, 46: 99-102.
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28:   Trejo-Guerra, R., E. Tlelo-Cuautle, J.M. Muñoz-Pacheco, C. Cruz-Hernandez and C. Sanchez-López, 2007. High-level simulation of chua’s circuit to verify frequency scaling behavior. Res. Comput. Sci., 29: 37-43.