Dr. Haridas Mangalam
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Dr. Haridas Mangalam

Professor and Head
Sri Ramakrishna Institute of Technology, India

Highest Degree
Ph.D. in VLSI Design and Testing from Anna University, Chennai, Tamil Nadu, India

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Area of Interest:

Computer Sciences
100%
Digital Communication
62%
Information Technology
90%
Programming
75%
VLSI Design
55%

Research Publications in Numbers

Books
0
Chapters
0
Articles
0
Abstracts
0

Selected Publications

  1. Kavitha, K. and H. Mangalam, 2016. Multilevel spatial modulation. J. Chinese Inst. Eng., 39: 713-721.
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  2. Kavitha, K. and H. Mangalam, 2016. Low complex decoding algorithm for multilevel space time trellis codes over MIMO channel. Int. J. Inf. Commun. Technol., 8: 69-78.
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  3. Gokila, D. and H. Mangalam, 2016. Programmable truncated multiplier. J. Comput. Theor. Nanosci., 13: 5046-5051.
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  4. Shanmugam, Y. and H. Mangalam, 2015. Review and performance evaluation of multiplexers using different logic styles for sub-micron technologies. Int. J. Applied Eng. Res., 10: 7261-7274.
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  5. Rajasekar, P. and H. Mangalam, 2015. Design and implementation of low power multistage aes s Box. Int. J. Appl. Eng. Res., 10: 40535-40540.
  6. Kalaiselvi, K. and H. Mangalam, 2015. Power efficient and high performance VLSI architecture for AES algorithm. J. Electr. Sys. Inf. Technol., 2: 178-183.
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  7. Kalaiselvi, K. and H. Mangalam, 2015. FPGA implementation and performance analysis of stream ciphers for cryptographic applications. Int. J. Appl. Eng. Res., 10: 34647-34651.
  8. Anushkannan, N.K. and H. Mangalam, 2015. Design of a CMOS PFD-CP module for a PLL. Sadhana, 40: 1105-1116.
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  9. Sivakumar, R. and H. Mangalam, 2014. Radar based vehicle collision avoidance system used in four wheeler automobile segments. Int. J. Sci. Eng. Res., 5: 763-770.
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  10. Sekar, C.P., Dr.H. Mangalam and S. Malathy, 2014. Load balanced reliable power aware multicast routing protocol for manets. Pensee J., Vol, 76 .
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  11. Kumar, S.S. and H. Mangalam, 2014. Removal of different types of artifacts and impulse noise in gray scale images. J. Theor. Applied Inf. Technol., 69: 305-317.
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  12. Kavitha, K. and H. Mangalam, 2014. Multilevel spatial multiplexing -space time trellis coded modulation system for fast fading mimo channel. Int. J. Eng. Technol., 6: 273-277.
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  13. Kalaiselvi, K., H. Mangalam and K. Manjunathan, 2014. Design of low power high speed adders using modified self-resetting logic. Middle East J. Sci. Res., 22: 829-834.
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  14. Kalaiselvi, K., H. Mangalam and K. Manjunathan, 2014. Design of area optimized high speed adder circuits in self resetting logic style. J. VLSI Signal Process., 4: 31-48.
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  15. Janeera K. and H. Mangalam, 2014. A new fast access low power multilevel cache architecture. Int. J. Innovative Res. Comput. Commun. Eng., 2: 5025-5031.
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  16. Gokila, D. and H. Mangalam, 2014. Implementation of configurable floating point multiplier. J. theor. Applied Inf. Technol., 64: 331-338.
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  17. Sivakumar, R. and H. Mangalam, 2013. Real time based ranging and detection of an adaptive cruise control in automobiles. Int. J. Res. Electr. Commun. Engg., Vol, 1 .
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  18. Prabhu, E., H. Mangalam and S. Karthick, 2013. A low power multiplier using encoding and bypassing technique. J. Theor. Appl. Inf. Technol. 57: 251-260.
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  19. Prabhu, E., H. Mangalam and K. Saranya, 2013. Design of low power digital fir filter based on bypassing multiplier. J. Comput. Appl. 70: 5-8.
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  20. Kalaiselvi, K. and H. Mangalam, 2013. Area efficient high speed and low power mac unit. Int. J. Comput. Appl., 67: 40-44.
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  21. Dharani, V.A., G. Divya, N. Esack, H. Mangalam and N.K. Anushkannan, 2013. Design of various PFD and charge-pump architectures for a PLL-a survey. Digital Signal Process. 5: 284-287.
  22. Kumar, S.S. and H Mangalam, 2012. Wavelet-based image compression of quasi encrypted grayscale images. Int. J. Comput. Appl. 45: 35-39.
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  23. Padmashini, R., K. Kavitha and Dr. H. Mangalam, 2011. Performance study of bicm-ofdm system over awgn and slow fading channel. Int. J. Adv. Commun. Eng. 3: 37-41.
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  24. Mangalam, H. and K. Gunavathi, 2007. Domino logic circuit with reduced leakage and improved noise margin. Int. J. Appl. Eng. Res., 2: 585-593.
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  25. Mangalam, H. and K. Gunavathi, 2006. Gate and subthreshold leakage reduced sram cells. Int. ICGST J. Digital Signal Process. 6: 51-55.
  26. Mangalam, H. and K. Gunavathi, 2006. Flipflops for low power and high speed performance. Int. AMSE J. Model. A. 79: 75-86.