Hi, I am U. Saravanakumar, My LiveDNA is 91.5402
 
   
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Dr. U. Saravanakumar
 
Highest Degree: Ph.D. in Network on Chip from PSG College of Technology, India
 
Institute: PSG College of Technology, India
 
Area of Interest: Computer Sciences
  •   VLSI Design
  •   System Level Design
  •   Digital Design
  •   Network on Chip
 
URL: http://livedna.org/91.5402
 
My SELECTED Publications
1:   Saravanakumar, U. and R. Rangarajan, 2012. Energy and throughput analysis of routing algorithms for 2D mesh Network on chip. Procedia Engin., 30: 144-151.
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2:   Saravanakumar, U. and R. Rangarajan, 2013. Design and performance evaluation of on chip network routers. J. Theor. Appl. Inf. Technol., 52: 211-218.
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3:   Saravanakumar, U. and R. Rangarajan, 2013. Simulation and analysis of multicast routing algorithm for 2-D mesh network on chip. Asian J. Sci. Res., 6: 754-762.
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4:   Saravanakumar, U., K. Rajasekar and R. Rangarajan, 2013. Implementation of Scheduling Algorithms for On Chip Communications. Int. J. Comput. Appl., 62: 35-38.
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5:   Saravanakumar, U., R. Rangarajan and K. Rajasekar, 2012. Hardware Implementation of Pipeline Based Router Design for On-Chip Network. CTACT J. Commun. Technol., 3: 646-650.
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6:   Saravanakumar, U., R. Rangarajan, R. Haripriya, R. Nithya and K. Rajasekar, 2013. Cluster based hierarchical routing algorithm for network on chip. Circuits Syst., 4: 401-406.
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7:   Vimal, S.P., M. Kasiselvanathan and U. Saravanakumar, 2013. A new SLM and PTS schemes for PAPR reduction in OFDM systems. Int. J. Adv. Res. Comput. Commun. Eng., 2: 4236-4240.
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