Biography

Dr. Naushad Alam is presently working as Assistant Professor at University Polytechnic, AMU, Aligarh, India. He has completed his Ph.D. in Microelectronics from Indian Institute of Technology Roorkee, Roorkee, Uttarakhand, India. His main area of interest focuses on Electronics Engineering. His area of expertise includes Electronic Circuit, PVT Variation, Low Power Circuit, Reliable Circuit Design Low Power SRAM, Delay Modeling, Robust SRAM Cell, and Circuit Simulation. He has published 5 research articles in journals as well as 22 papers in national and international conferences contributed as author/co-author.

Area of Interest:

Engineering

100%

Electronic Engineering

62%

Low Power Circuit

90%

Electronic Circuit

75%

Circuit Simulation

55%

Research Publications in Numbers

Books
0

Chapters
0

Articles
0

Abstracts
0

Selected Publications

Kaur, B., N. Alam, S.K. Manhas and B. Anand, 2014. Efficient ECSM characterization considering voltage, temperature and mechanical stress variability. IEEE Trans. Circuits Syst. I Regul. Pap., 61: 3407-3415.
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Alam, N., B. Anand and S. Dasgupta, 2014. An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit design. IEEE Trans. Circuits Syst. I Regul.Pap., 61: 1714-1726.
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Alam, N., B. Anand and S. Dasgupta, 2013. The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab., 53: 379-385.
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Alam, N., B. Anand and S. Dasgupta, 2013. The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab., 53: 718-724.
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Alam, N., B. Anand and S. Dasgupta, 2012. Gate-pitch optimization for circuit design using strain-engineered multifinger gate structures. IEEE Trans. Electron Devices, 59: 3120-3123.
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