1. Singh, I.V., M.S. Alam and G.A. Armstrong, 2016. GHz Range Frequency Characterization of Moderately Inverted Sub-100 nm Gate Underlap Silicon-on-Insulator-Metal-Oxide-Semiconductor Field Effect Transistors. J. Nanoelectron. Optoelectron., 11: 514-522.
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2. Singh, I.V. and M.S. Alam, 2015. Quantum effects investigation in 20 nm gate underlap SOI MOSFET for millimeter wave applications. Nanosci. Nanoeng., 3: 19-24.
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3. Singh, I.V. and M.S. Alam, 2015. Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN. Radioelectron. Commun. Syst., 58: 191-200.
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4. Singh, I.V. and M.S. Alam, 2015. Analog/RF performance investigation of nanoscale gate-underlap single and double gate silicon-on-insulator MOSFETs with high-k stack on spacer. J. Nanoelectron. Optoelectron., 10: 790-794.
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5. Kumar, G.L. and I.V. Singh, 2015. Mixed convective heat transfer flow over two circular cylinder in tandem arrangement. J. Basic Appl. Eng. Res., Vol. 2. .
6. Singh, I.V. and M.S. Alam, 2014. Design of Nano-Scale SOI-MOSFETs for Low Power GHz Wireless Systems. LAP LAMBERT Academic Publishing, Sarbrucken, Germany., ISBN: 978-3-659-63541-0, Pages: 220..
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7. Singh, I.V., M.S. Alam and G.A. Armstrong, 2013. Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications. Radioelectron. Commun. Syst., 56: 265-277.
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8. Singh, I.V., 2013. Spacer optimization and accurate small-signal modeling of 90nm gate underlap SOI-MOSFETs for low power GHz applications. Int. J. Nano Devices Sens. Syst. (IJ-Nano), Vol. 2. .
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9. Singh, I.V. and M.S. Alam, 2011. Design and optimization of nano-scale double gate SOI-MOSFETs for analog applications. J. Electron. Des. Technol., Vol. 2. .
10. Singh, I.V. and M.S. Alam, 2011. Comparative study of noise performance in single and double gate nano scale SOI MOSFETs using SILVACO TCAD. MIT Int. J. Electron. Commun. Eng., 1: 36-39.
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11. Singh, I.V. and M.S. Alam, 2011. Comparative study of analog performance of nano scale single and double gate SOI MOSFETs. National J. Technol., Vol. 7. .
12. Singh, I.V. and M.S. Alam, 2010. Nano scale single and double gate SOI MOSFETs structures and compression of electrical performance factors. Int. J. Comput. Applic., 7: 5-11.
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