Dr. Maheswari Murali

Professor
K. Ramakrishnan College of Engineering, India

Highest Degree
Ph.D. in VLSI System from Anna University, India

My URL
https://livedna.org/91.13178

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Area of Interest:

Computer Sciences
Network on Chip
VLSI
System Design
Topology

Selected Publications

  1. Vimal, S. and M. Maheswari, 2016. Design and performance improvement of a low noise amplifier with different matching techniques and stability network. Int. J. Eng. Res. Sci., 2: 1-10.

  2. Vimal, S. and M. Maheswari, 2015. Improved design of RF BJT low noise amplifier for 5 to 6 GHz frequency range. Int. J. Applied Eng. Res., 10: 19970-19973.

  3. Ramya, S., M. Maheswari and J. Saranya, 2015. Design of frequency reconfigurable low profile patch antenna. Int. J. Applied Eng. Res., 10: 20007-20010.

  4. Maheswari, M., 2015. Design of reliable custom topology for application specific network on chip. Int. J. Adv. Res. Electr. Electron. Instrumentation Eng., 4: 4039-4046.

  5. Maheswari, M. and T.M. Rosy, 2015. Design of an improved Finite Impulse Response (FIR) filter using vedic multiplier. Programmable Device Circuits and Syst., 7: 113-118.
    Direct Link  |  

  6. Hemalatha, B., M. Maheswari and R. Balamurugan, 2015. Design of cascaded integrator comb filter for signal processing application. Int. J. Applied Eng. Res., 10: 20011-20014.

  7. Maheswari, M. and V. Srinivasan, 2014. New methodology for the enhancement of spectral amplitude coding-optical code division multiple access (SAC-OCDMA) system and its performance measures. Int. J. Emerg. Technol. Comput. Sci. Electron., 7: 207-210.

  8. Maheswari, M. and G. Seetharaman, 2014. Enhanced low complex double error correction coding with crosstalk avoidance for reliable on-chip interconnection link. J. Electron. Testing, 30: 387-400.
    CrossRef  |  Direct Link  |  

  9. Maheswari, M. and G. Seetharaman, 2014. Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link. Int. J. Comput. Applic. Technol., 49: 80-88.
    CrossRef  |  Direct Link  |  

  10. Maheswari, M., 2013. A novel custom topology generation for application specific network-on-chip using genetic algorithm optimization technique. J. Artifi. Intelli., 6: 8-21.
    CrossRef  |  

  11. Maheswari, M. and G. Seetharaman, 2013. Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links. Microprocessors Microsyst., 37: 420-429.
    CrossRef  |  Direct Link  |  

  12. Maheswari, M. and G. Seetharaman, 2013. Hamming Product code based multiple bit error correction coding scheme using keyboard scan based decoding for on chip interconnects links. Applied Mech. Mater. J., 241-244: 2457-2461.
Member since October, 2016